Microelectronic devices, such as memory devices, microprocessors, and light emitting diodes, typically include one or more semiconductor dies mounted to a substrate and encased in a protective covering. The semiconductor dies include functional features, such as memory cells, processor circuits, interconnecting circuitry, etc. Semiconductor die manufacturers are under increasing pressure to reduce the volume occupied by semiconductor dies and yet increase the capacity and/or speed of the resulting encapsulated assemblies. To meet these demands, semiconductor die manufacturers often stack multiple semiconductor dies vertically on top of each other to increase the capacity or performance of a microelectronic device within the limited volume on the circuit board or other element to which the semiconductor dies are mounted.
The stacked semiconductor dies are typically electrically connected by solder bumps that are attached to metal pillars formed on bond pads of the dies. Often, the bond pads of each semiconductor die are spaced closely together such that when solder is reflowed during the stacking process to form the solder bumps, the solder can sometimes “bridge” between adjacent metal pillars to electrically connect adjacent ones of the pillars and short the semiconductor device. Conventional methods for inhibiting solder bridging include relaxing the pillar pitch by forming a redistribution layer (RDL) on the semiconductor dies to redistribute the electrical connections to the bond pads. Alternatively, the semiconductor dies can be re-designed such that the bonds pads of each die have a greater pitch. However, both of these methods can increase the cost and/or complexity of designing and manufacturing a semiconductor device.